Interrupts

The VME10 SCM interrupt prioritizer is implemented.

VME10 device interrupts are generated, and asserted based on the device's own masks, but not serviced  by the VME10's interrupt prioritizer, unless NOT masked (in a SCM control register). The prioritizer uses several Mask bits found in various SCM registers. Setting a mask inhibits the associated interrupt from being processed by the CPU, even if already asserted (but not processed yet).  Clearing a mask, allows an interrupt to be processed by the CPU, if pending.

TIMIMSK*  - mc68hc18 RTC
DMAIMSK*  - (not implemented)
RXRDYMSK* - SN2661 EPCI Recieve Ready (used by keyboard)
SYSFMSK*  - (not implemented)
BCLRMSK*  - (not implemented)
TXRDYMSK* - SN2661 EPCI Tranmit Ready (used by keyboard)
MMUIMSK*  - 68451 Binary Segmented MMU

IMASK*    - Global interrupt mask - masks everything
INTMSK4*  - IOC interrupt 4 (mvme400)
INTMSK3*  - IOC interrupt 3 (rwin)
INTMSK2*  - IOC interrupt 2
INTMSK1*  - IOC interrupt 1 (mvme410)

IRQ7MSK*  -
IRQ6MSK*  -
IRQ5MSK*  -
IRQ4MSK*  -  (none implemented)
IRQ3MSK*  -
IRQ2MSK*  -
IRQ1MSK*  -
VBIAMSK*  -

IO Channel interrupts are implemented.

IOC interrupts (1-4) are generated ,onboard an IOC card, based on the device's own masks. When an Interrupt is Asserted or de-asserted, the IOC interrupts are wire-or'ed, and if any is pending, the appropriate VME10 interrupt is set pending. If none are pending, then the VME10 interrupt is cleared. The CPU will detect and process an interrupt, if not masked by an SCM control register interrupt mask (IMASK*, INTMSK4*, INTMSK3*, INTMSK2*, INTMSK1*) and not masked by the CPU.

The jumpers for the Interrupts can be set in the emulator using a dialog, BUT.....
WARNING  -  Changing the interrupt while the emulator is running is not recommended.
	    It is possible to change the interrupt after it is asserted and before it is acknowledged. 
	    This will lock the Interrupt asserted, and it can not be un-asserted. 

Change the interrupts only while the emulator is stopped. PLAN ON restarting the emulator before using. 

IOC base address = 0xF1C000 
		Factory Defaults   Required for VME10

 0-3  RWIN             +$68		 +$68		0xf1c0d1
  0  Rwin Data     - IOCINT3		IOCINT3
  1  Rwin Command  - IOCINT3		IOCINT3
  2  n/a
  3  n/a

 4-7  MVME400-card 1   +$E0		 +$E0		0xf1c1c1
  4  Nec7201 int   - IOCINT3		IOCINT4
  5  PIA IRQA      - IOCINT3		IOCINT4
  6  PIA IRQB      - IOCINT3		IOCINT4
  7  n/a

 8-11 MVME400-card 2   +$d0		 +$d0		0xf1c1A1
  8   Nec7201 int  - IOCINT3		IOCINT4
  9   PIA IRQA     - IOCINT3		IOCINT4
  10  PIA IRQB     - IOCINT3		IOCINT4
  11  n/a

 12-15 MVME410         +$F0		 +$F0		0xF1C1E1
  12  PIA-1 IRQA   - IOCINT1		IOCINT1
  13  PIA-1 IRQB   - IOCINT2		IOCINT1
  14  PIA-2 IRQA   - IOCINT3		IOCINT1
  15  PIA-2 IRQB   - IOCINT1		IOCINT1

IOCVEC1   = $41          I/O channel interrupt 1 vector.
IOCVEC2   = $43          I/O channel interrupt 2 vector.
IOCVEC3   = $44          I/O channel interrupt 3 vector.
IOCVEC4   = $45          I/O channel interrupt 4 vector.
*
IOCLVL1   = 2            I/O channel interrupt 1 level.
IOCLVL2   = 4            I/O channel interrupt 2 level.
IOCLVL3   = 5            I/O channel interrupt 3 level.
IOCLVL4   = 6            I/O channel interrupt 4 level.

The Visual Basic runtime is not capable of generating periodic events (interrupts) except in 55 ms increments. This makes the versados periodic timer un-reliable.