-DISASSEMBLER

The following instructions required special handling in the disassembler

TRAP, BKPT, MOVES, MOVEC, MOVEM, LINK, UNLK, 
MOVE USP, BRA, BCC, DBCC, 
ANDI CCR, ORI CCR, EORI CCR
ANDI SR, ORI SR, EORI SR
MOVE CCR, MOVE SR,
RTD , STOP

LPSTOP, TBLS, TBLSN, TBLU, TBLUN, DIVUSL, MULUSL, CHK2, CMP2

NOTE - the LINK instruction violates the generic rules, and has SRC defined instead of DST, but used like that everywhere - it is important---done like that because Immediate can not be destination in mcrGetDop, however, LINK does not use mcrGetDop. It does all accesses in its own microcode.. mcrLink)

The following instructions use the instruction format field in the disassembler

RTS, RTR, NOP, RTE, ILLEGAL, TRAPV, RESET, BGND

All others are genericly disassembled based on SRC and DST modes and registers that are valid as specified in the OpMap(OpCODE).Disassemble field...

Invalid instruction are printed as the hex opcode in parenthesis. Invalid CPU32 instructions are not flagged as illegal, if illegality is in second word of instruction.. ( Execution Unit DOES flag as ILL )

The 64k entry Opcode MAp is used both for execution and disassembly.

The Opcode Map is created at startup(defaults to MC68010) or each time the CPU type is changed. Each instruction opcode is decoded and the decoded info is put in the entry, corresponding to the opcode value, by using the opcode as an index to the array of records. Each record contains SRC/DST Register/Mode fields. Also an ExtraValue used to hold stuff like quick immediate values and inherent data from the opcode. Also, an ExtraInfo field that contains stuff like Condition, direction, instruction mode, etc.  This decoding is done for every opcode so that there's no need to decode at execution time. The OPcode map also contains info used by the disassembler. 

There's also a 64k Extension word map for the addressing mode, Address Register Indirect with Index and Displacment. The entire gammut is decoded at startup and the inherent displacement, and index register info is put there, so no need to decode at execution time. CPU32 Base displacement are correctly disassembled, when the CPU type is CPU32. If the CPU type is NOT CPU32, then bits associated with Base Displacement are ignored by the disassembler.(Execution unit also ingores them..as would a real mc68000 or mc68010 ....There is a different CalcSEA and CalcDEA microcode routine for MC68xxx and for CPU32. )

